// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2019 BayLibre, SAS
 * Author: Neil Armstrong <narmstrong@baylibre.com>
 */

/dts-v1/;

#include "meson-sm1.dtsi"
#include "meson-khadas-vim3.dtsi"

/ {
	compatible = "khadas,vim3l", "amlogic,sm1";
	model = "Khadas VIM3L";

	vddcpu: regulator-vddcpu {
		/*
		 * Silergy SY8030DEC Regulator.
		 */
		compatible = "pwm-regulator";

		regulator-name = "VDDCPU";
		regulator-min-microvolt = <690000>;
		regulator-max-microvolt = <1050000>;

		vin-supply = <&vsys_3v3>;

		pwms = <&pwm_AO_cd 1 1250 0>;
		pwm-dutycycle-range = <100 0>;

		regulator-boot-on;
		regulator-always-on;
	};
};

&cpu0 {
	cpu-supply = <&vddcpu>;
	operating-points-v2 = <&cpu_opp_table>;
	clocks = <&clkc CLKID_CPU_CLK>;
	clock-latency = <50000>;
};

&cpu1 {
	cpu-supply = <&vddcpu>;
	operating-points-v2 = <&cpu_opp_table>;
	clocks = <&clkc CLKID_CPU1_CLK>;
	clock-latency = <50000>;
};

&cpu2 {
	cpu-supply = <&vddcpu>;
	operating-points-v2 = <&cpu_opp_table>;
	clocks = <&clkc CLKID_CPU2_CLK>;
	clock-latency = <50000>;
};

&cpu3 {
	cpu-supply = <&vddcpu>;
	operating-points-v2 = <&cpu_opp_table>;
	clocks = <&clkc CLKID_CPU3_CLK>;
	clock-latency = <50000>;
};

&pwm_AO_cd {
	pinctrl-0 = <&pwm_ao_d_e_pins>;
	pinctrl-names = "default";
	clocks = <&xtal>;
	clock-names = "clkin1";
	status = "okay";
};
